It is common to employ multiple layers of interconnections as a part of complex integrated circuits (ICs). As used herein, the term “integrated circuit” and the abbreviation “IC”, singular or plural, are intended to include any electronic system employing monolithic multi-layer interconnections whether formed on a semiconductor substrate or not. Generally, each level of the multi-layered interconnections consists of a first level of electrical conductors, e.g., identified as conductors MN, covered by a dielectric interlayer above which is a second level of conductors, e.g., identified as conductors MN+1, with various conductor filled vias, e.g., identified as VN+1/N, extending between the two conductor levels MN+1 and MN, thereby electrically coupling some of the conductors MN+1 to some of conductors MN that lie one above the other. The index N identifies the particular interconnection level in the stack of interconnection levels being referred to. As the feature sizes of the various devices and other elements within the IC are shrunk in order to achieve every more complex IC functions, packing density limitations that may be imposed by the multilayer interconnections and failure mechanisms that may arise therefrom are of greater concern.